Method of producing semiconductor integrated circuit device and semiconductor integrated circuit device

ABSTRACT

A sidewall insulating film ( 11 ) made of a silicon oxide film is formed on the sidewall of a gate electrode ( 7 ) (word line) with an aim to reduce the capacitance to the word line serving as the major component of the bit line capacitance. Also, when openings for connecting the bit lines are formed above the spaces of the gate electrodes ( 7 ) (word lines) by the dry etching of a silicon oxide film ( 31 ) above contact holes ( 12 ), a silicon nitride film ( 19 ) to be an etching stopper is provided below the silicon oxide film ( 31 ) so as to reduce the amount of the bottom surface of the opening receded below the upper surface of a cap insulating film ( 9 ). A side-wall insulating film ( 11 ) composed of a silicon oxide film is formed on the side wall of a gate electrode ( 7 ) (word line WL) to reduce pair word line capacity components as a main component of a bit line capacity. When a silicon oxide film ( 31 ) at the upper portion of a contact hole ( 12 ) is dry-etched to form a bit line connecting hole in the upper part of the gate electrode&#39;s ( 7 ) (word line WL) space, a nitride silicon film ( 19 ) working as an etching stopper is provided on the lower layer of the silicon oxide film ( 31 ) so as to reduce that portion of the bottom of the hole which sinks below the top surface of a cap insulating film ( 9 ).

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor integratedcircuit device and a manufacturing technique thereof. More particularly,the present invention relates to a technique effectively applied to asemiconductor integrated circuit device with DRAM (Dynamic Random AccessMemory) and its manufacture.

BACKGROUND ART

[0002] In the manufacturing process of the semiconductor integratedcircuit device, when forming openings by the etching of a silicon oxidefilm deposited on a semiconductor substrate, a silicon nitride film isprovided between an upper silicon oxide film and a lower silicon oxidefilm and the silicon nitride film is used as an etching stopper in orderto prevent the excessive etching of the lower silicon oxide film exposedon the bottom of the openings (e.g., in the gazette of Japanese PatentApplication Laid-Open No. 11-26574, and the like).

[0003] Also, in the manufacturing process of the large capacity DRAM inrecent years, the self align contact (SAC) technique (e.g., in thegazette of Japanese Patent Application Laid-Open No. 9-252098) has beenadopted. In this technique, when openings for connecting bit lines andcapacitors to a semiconductor substrate are formed in the miniaturizedspaces of word lines, a silicon nitride film is used to form theinsulating film covering the upper portion of the word line (capinsulating film) and the insulating film for covering the sidewallthereof (sidewall insulating film) so that the openings are formed in aself alignment manner with the spaces of the word lines by utilizing thedifference in etching rate between the silicon oxide film and thesilicon nitride film.

[0004] Also, the gazette of the Japanese Patent Application Laid-OpenNo. 2000-77622 relates to the DRAM in which the cap insulating film andthe sidewall insulating film of the word line are formed of a siliconoxide film. However, it discloses the technique as follows. That is, inorder to prevent the sidewall insulating film made of a silicon oxidefilm from being etched when forming the openings by the etching of theinterlayer insulating film on the word line, the interlayer insulatingfilm is formed of a silicon nitride film and a silicon oxide film formedthereon so that the underlying silicon nitride film functions as theetching stopper.

DISCLOSURE OF THE INVENTION

[0005] In the development of 256 Mbit DRAM and 1 Gbit DRAM, the inventorof the present invention has examined the reduction of the bit-linecapacitance as one solution to increase the refresh time interval.

[0006] The components of the bit-line capacitance are, for example, thecapacitance to the adjacent bit lines, the capacitance to the substrate,the capacitance to the storage electrode, the capacitance to the wordline, and the capacitance to the plate electrode. However, in the caseof the memory cell having a so-called capacitor over bit line (COB)structure in which a data storage capacitor is provided on the bit line,since the distance between the bit line and the word line is short, thecapacitance to the word line is the largest component of the bit linecapacitance. Therefore, the reduction of the capacitance to the wordline becomes the top priority for the reduction of the bit linecapacitance.

[0007] As described above, in the conventional manufacturing processusing the self align contact (SAC) technique, the upper portion and thesidewall of the word line are covered with a silicon nitride film havingthe etching selectivity higher than that of the silicon oxide film.However, since the relative dielectric constant of the silicon nitridefilm is about twice as high as that of the silicon oxide film, thecapacitance to the word line in the bit line capacitance is increased ifthe upper portion and the sidewall of the word line are covered with thesilicon nitride film.

[0008] Meanwhile, in the case where the sidewall insulating film and thecap insulating film of the word line are formed of a silicon oxide filmwith an aim to reduce the capacitance to the word line in the bit linecapacitance, the sidewall insulating film or the cap insulating film isexcessively etched when forming the openings (contact holes) forconnecting the bit lines and the substrate in the spaces of the wordlines, and hence, the bottom of the opening comes close to the wordline. Consequently, the capacitance to the word line in the bit linecapacitance is increased also in this case.

[0009] An object of the present invention is to provide a techniquecapable of reducing the bit-line capacitance of the DRAM with aminiaturized memory cell size.

[0010] The above and other objects and novel characteristics of thepresent invention will be apparent from the description and theaccompanying drawings of this specification.

[0011] The typical ones of the inventions disclosed in this applicationwill be briefly described as follows.

[0012] The semiconductor integrated circuit device according to thepresent invention comprises: a plurality of first conductor piecesextending parallel to each other over a semiconductor substrate; firstsidewall insulating films made of a silicon oxide film formed onsidewalls of said first conductor pieces; second conductor pieces formedbetween said first conductor pieces; a first insulating film made of asilicon nitride film formed over said plurality of first and secondconductor pieces; and a second insulating film made of a silicon oxidefilm formed over said first insulating film, wherein first openings areformed in said first and second insulating films above each of saidplurality of second conductor pieces, and third conductor pieceselectrically connected to said second conductor pieces are formed insaid first openings.

[0013] The method of manufacturing a semiconductor integrated circuitdevice according to the present invention comprises the steps asfollows.

[0014] That is, it comprises the steps of: forming first conductorpieces over a semiconductor substrate and forming a first insulatingfilm over the first conductor pieces and the semiconductor substrate;forming first openings in said first insulating film so as to be locatedat positions between said first conductor pieces and then forming firstsidewall insulating films made of a silicon oxide film on sidewalls ofsaid first openings; forming second conductor pieces in said firstopenings; forming a second insulating film made of a silicon nitridefilm over said first and second conductor pieces and forming a thirdinsulating film made of a silicon oxide film over said second insulatingfilm; and forming second openings in said third insulating film and saidsecond insulating film over said first openings to expose said secondconductor pieces at the bottom of said second openings, then formingthird conductor pieces electrically connected to said second conductorpieces in said second openings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is an entire plan view showing the semiconductor chip onwhich the DRAM according to an embodiment of the present invention isformed;

[0016]FIG. 2 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the structure of the DRAMaccording to an embodiment of the present invention;

[0017]FIG. 3 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the structure of the DRAMaccording to an embodiment of the present invention;

[0018]FIG. 4 is a plan view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0019]FIG. 5 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0020]FIG. 6 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0021]FIG. 7 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0022]FIG. 8 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0023]FIG. 9 is a plan view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0024]FIG. 10 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0025]FIG. 11 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0026]FIG. 12 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0027]FIG. 13 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0028]FIG. 14 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0029]FIG. 15 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0030]FIG. 16 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0031]FIG. 17 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0032]FIG. 18 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0033]FIG. 19 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0034]FIG. 20 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0035]FIG. 21 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0036]FIG. 22 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0037]FIG. 23 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0038]FIG. 24 is a plan view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0039]FIG. 25 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0040]FIG. 26 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0041]FIG. 27 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0042]FIG. 28 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0043]FIG. 29 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0044]FIG. 30 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0045]FIG. 31 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0046]FIG. 32 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0047]FIG. 33 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0048]FIG. 34 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0049]FIG. 35 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0050]FIG. 36 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0051]FIG. 37A is a schematic plan view of a contact hole formed by theuse of an etching resistant mask having a slit-shaped (trench-shaped)opening, FIG. 37B is a schematic plan view of a contact hole formed bythe use of an etching resistant mask having a hole-shaped opening, andFIG. 37C is a schematic plan view of a contact hole formed by the use ofan etching resistant mask having a hole-shaped opening;

[0052]FIG. 38 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0053]FIG. 39 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0054]FIG. 40 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0055]FIG. 41 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0056]FIG. 42 is a plan view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0057]FIG. 43 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0058]FIG. 44 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0059]FIG. 45 is a sectional view used to explain the problem examinedby the inventor of the present invention;

[0060]FIG. 46 is a sectional view used to explain the problem examinedby the inventor of the present invention;

[0061]FIG. 47 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0062]FIG. 48 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0063]FIG. 49 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0064]FIG. 50 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0065]FIG. 51 is a plan view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0066]FIG. 52 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0067]FIG. 53 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0068]FIG. 54 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0069]FIG. 55 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0070]FIG. 56 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0071]FIG. 57 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0072]FIG. 58 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to an embodiment of the present invention;

[0073]FIG. 59 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to another embodiment of the present invention;

[0074]FIG. 60 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to another embodiment of the present invention;

[0075]FIG. 61 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to another embodiment of the present-invention;

[0076]FIG. 62 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to another embodiment of the present invention;

[0077]FIG. 63 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0078]FIG. 64 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0079]FIG. 65 is a plan view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0080]FIG. 66 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0081]FIG. 67 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0082]FIG. 68 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0083]FIG. 69 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0084]FIG. 70 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0085]FIG. 71 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0086]FIG. 72 is a sectional view- showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0087]FIG. 73 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0088]FIG. 74 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0089]FIG. 75 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0090]FIG. 76 is a plan view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0091]FIG. 77 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0092]FIG. 78 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention;

[0093]FIG. 79 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention; and

[0094]FIG. 80 is a sectional view showing the principal part of asemiconductor substrate, which illustrates the manufacturing method ofDRAM according to still another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0095] Hereinafter, embodiments of the present invention will bedescribed in detail with reference to the accompanying drawings. Notethat components having the same function are denoted by the samereference symbols throughout the drawings for describing the embodiment,and the repetitive description thereof is omitted.

First Embodiment

[0096]FIG. 1 is an entire plan view of a semiconductor chip 1A on whichthe DRAM (Dynamic Random Access Memory) according to this embodiment isformed.

[0097] A DRAM with a memory capacity of 256 Mbit is formed on the mainsurface of the rectangular semiconductor chip 1A. This DRAM includes amemory section comprised of a plurality of memory arrays (MARY) andperipheral circuits (PC) arranged in the periphery of the memory arrays.Also, a plurality of bonding pads BP to which the wires and bumpelectrodes are connected are arranged in a row in the center of thesemiconductor chip 1A.

[0098]FIG. 2 is a sectional view of a semiconductor substrate (referredto as a substrate hereinafter) showing one end portion of the memoryarray (MARY).

[0099] For example, a p-type well 2 is formed on the main surface of thesubstrate 1 made of p-type single crystal silicon, and device isolationtrenches 4 are formed in the p-type well 2. A plurality of memory cellsare formed in the active regions of the p-type well 2 defined by thedevice isolation trenches 4. Each of the memory cells includes onememory cell selecting MISFET (Metal Insulator Semiconductor Field EffectTransistor) Qt comprised of an n-channel MISFET and one data storagecapacitor C formed on the MISFET Qt. The memory cell selecting MISFET Qtis constituted of a gate insulating film 6, a gate electrode 7 servingas a word line WL in the region other than the active region, and a pairof n-type semiconductor regions (source and drain regions) 8. The gateelectrode 7 (word line WL) is comprised of a three-layered conductivefilm formed by laminating an n-type polycrystalline silicon film dopedwith P (phosphorus), a WN (tungsten nitride) film, and a W (tungsten)film.

[0100]FIG. 3 is a sectional view of the substrate 1 showing a part ofthe peripheral circuit (PC) section. The p-type well 2 and an n-typewell 3 are formed on the substrate 1 in the peripheral circuit (PC)section. An n-channel MISFET Qn is formed in the active region of thep-type well 2, and a p-channel MISFET Qp is formed in the active regionof the n-type well 3. The n-channel MISFET Qn is mainly comprised of thegate insulating film 6, the gate electrode 7, and a pair of n⁺-typesemiconductor regions (source and drain regions) 17, and the p-channelMISFET Qp is mainly comprised of the gate insulating film 6, the gateelectrode 7, and a pair of P⁺-type semiconductor regions (source anddrain regions) 18. More specifically, the peripheral circuit (PC) iscomprised of a complementary MISFET obtained by combining the n-channelMISFET Qn and the p-channel MISFET Qp.

[0101] As shown in FIG. 2, two-layered sidewall insulating films 10 and11 are formed on the sidewalls of the gate electrodes 7 (word lines WL)of the memory cell selecting MISFETs Qt. The outer sidewall insulatingfilm 11 is made of, for example, a silicon oxide film with a thicknessof about 30 nm, and the inner sidewall insulating film 10 is made of asilicon nitride film with a thickness larger than that of the firstsidewall insulating film 11 (for example, about 10 nm to 15 nm). Theheight of the sidewall insulating film 11 made of a silicon oxide filmis higher than that of the upper surface of the gate electrode 7 (wordline WL) and lower than that of the upper end portion of the capinsulating film 9 which covers the upper portion of the gate electrode 7(word line WL).

[0102] Contact holes (openings) 12 and 13 surrounded by the two-layeredsidewall insulating films 10 and 11 are formed in the spaces of the gateelectrodes 7, and plugs (conductive layers) 14 made of an n-typepolycrystalline silicon film doped with P (phosphorus) are filled intothe contact holes 12 and 13.

[0103] Two insulating films (silicon nitride film 19 and silicon oxidefilm 31 in this order from below) are formed over the upper portion ofthe memory cell selecting MISFET Qt, and bit lines BL for writing andreading data to the memory cell are formed on the silicon oxide film 31.The bit line BL is made of, for example, a metal film such as a W(tungsten) film. The bit line BL is electrically connected to one of then-type semiconductor regions (source and drain regions) 8 of the memorycell selecting MISFET Qt via the through hole 32 formed in the siliconoxide film 31 and the silicon nitride film 19 and the underlying contacthole 12. Plugs 33 made of a metal film obtained by, for example,laminating a W film on a TiN film are filled into the through holes 32.

[0104] A silicon oxide film 34 and a silicon nitride film 35 are formedover the bit lines BL, and data storage capacitors C are formed on thesilicon nitride film 35. The data storage capacitor C is comprised of alower electrode 41 formed in a deep trench 40 formed by etching a thicksilicon oxide film 39 on the silicon nitride film 35, a capacitorinsulating film 42 formed on the lower electrode 41, and an upperelectrode 43.

[0105] The lower electrode 41 of the data storage capacitor C is madeof, for example, a Ru (ruthenium) film, and is electrically connected tothe other of the n-type semiconductor regions (source and drain regions)8 of the memory cell selecting MISFET Qt via the through hole 36 and theunderlying contact hole 13. The capacitor insulating film 42 is made of,for example, a BST (Ba_(x)Sr_(1−x)TiO₃: Barium Strontium Titanate) film,and the upper electrode 43 is made of, for example, an Ru film. An Alalloy wiring 52 is formed on the data storage capacitor C via a siliconoxide film 51.

[0106] As shown in FIG. 3, two-layered sidewall insulating films 10 and21 are formed on the sidewalls of the n-channel MISFET Qn and thep-channel MISFET Qp in the peripheral circuit (PC) section. The outersidewall insulating film 21 is made of, for example, a silicon oxidefilm with a thickness of about 70 nm, and the inner sidewall insulatingfilm 10 is made of the same silicon nitride film as that of theabove-described sidewall insulating film 10 of the memory cell selectingMISFET Qt.

[0107] First layer wirings 44 and 45 are formed over the n-channelMISFET Qn, and first layer wirings 46 and 47 are formed over thep-channel MISFET Qp. These first layer wirings 44 to 47 are made of thesame metal film as that of the above-described bit line BL, and areformed simultaneously with the bit line BL.

[0108] The first layer wirings 44 and 45 are electrically connected tothe n⁺-type semiconductor regions (source and drain regions) 17 of then-channel MISFET Qn via the contact holes 48 formed in the underlyinginsulating films (silicon oxide film 31, silicon nitride film 19, andsilicon oxide film 22). Also, the first layer wirings 46 and 47 areelectrically connected to the p⁺-type semiconductor regions (source anddrain regions) 18 of the p-channel MISFET Qp via the contact holes 49formed in the underlying insulating films (silicon oxide film 31,silicon nitride film 19, and silicon oxide film 22). The plugs 33 madeof a metal film obtained by, for example, laminating a W film on a TiNfilm are filled into the contact holes 48 and 49.

[0109] The silicon oxide film 34, the silicon nitride film 35, thesilicon oxide film 39 with a large thickness, and the silicon oxide film51 are formed on the first layer wirings 44 to 47 in this order frombelow, and Al alloy wirings 53 and 54 serving as second layer wiringsare formed on the silicon oxide film 51. The Al alloy wiring 53 iselectrically connected to the first layer wiring 44 via the through hole55 formed in the underlying insulating films (silicon oxide film 51,silicon oxide film 39, silicon nitride film 35, and silicon oxide film34). A plug 56 made of, for example, a metal film obtained by laminatinga W film on a TiN film is filled into the through hole 55.

[0110] Next, the manufacturing method of the DRAM constituted asdescribed above according to this embodiment will be described withreference to FIGS. 4 to 58 along the manufacturing process.

[0111] First, as shown in FIG. 4 (plan view showing one end portion ofthe memory array), FIG. 5 (sectional view taken along the line A-A inFIG. 4), and FIG. 6 (sectional view showing a part of the peripheralcircuit section), the device isolation trench 4 is formed in the deviceisolation region on the main surface of the substrate 1. The deviceisolation trench 4 is formed in the following manner. That is, the mainsurface of the substrate 1 is etched to form a trench with a depth ofabout 300 to 400 nm, and then, a silicon oxide film 5 with a thicknessof about 600 nm is deposited on the substrate 1 and in this trench bythe CVD method. Thereafter, the unnecessary silicon oxide film 5 outsidethe trench is polished and removed by the chemical mechanical polishing(CMP) method. As shown in FIG. 4, by forming the device isolation trench4, a large number of active regions L with elongated island-shapedpattern surrounded by the device isolation trench 4 are formed in thememory array.

[0112] Next, as shown in FIG. 7 (sectional view showing one end portionof the memory array), and FIG. 8 (sectional view showing a part of theperipheral circuit section), B (boron) is ion-implanted into a part ofthe substrate 1 and P (phosphorus) is ion-implanted into the other partthereof. Thereafter, the thermal treatment is performed to the substrate1 so as to diffuse these impurities in the substrate 1, thereby formingthe p-type well 2 and the n-type well 3.

[0113] Next, as shown in FIGS. 9, 10, and 11, the gate insulating film 6made of silicon oxide with a thickness of about 6 to 7 nm is formed onthe respective surfaces of the p-type well 2 and the n-type well 3 bythe thermal oxidation of the substrate 1. Subsequently, the gateelectrodes 7 of the memory cell selecting MISFET Qt, that of then-channel MISFET Qn, and that of the p-channel MISFET Qp are formed onthe gate insulating film 6. The gate electrodes 7 are formed in thefollowing manner. That is, an n-type polycrystalline silicon film dopedwith P (phosphorus) with a thickness of about 70 nm is deposited on thegate insulating film 6 by the CVD method, and then, a WN (tungstennitride) film with a thickness of about 5 nm and a W (tungsten) filmwith a thickness of about 60 nm are deposited thereon by the sputteringmethod. Subsequently, a cap insulating film 9 with a thickness of about200 nm is deposited further thereon. Thereafter, these films aredry-etched with using a photoresist film as a mask. The cap insulatingfilm 9 is made of a silicon nitride film (or laminated film of a siliconoxide film and a silicon nitride film). It is also possible to form thegate electrode 7 by using a polycide film (laminated film of apolycrystalline silicon film and a refractory metal silicide film).

[0114] As shown in FIG. 9, the gate electrodes 7 of the memory cellselecting MISFETs Qt constitute the word lines WL in the regions otherthan the active regions L and extend in a direction oblique to thelonger side of the active regions L. The gate length of the gateelectrode 7 of the memory cell selecting MISFET Qt is, for example,about 0.13 to 1.4 μm, and the space between the adjacent gate electrodes7 (word lines WL) is, for example, about 0.12 μm.

[0115] Next, as shown in FIGS. 12 and 13, the n-type semiconductorregions (source and drain regions) 8 are formed in the p-type well 2 ofthe memory array by the ion implantation of As (arsenic) into the p-typewell 2, and n⁻-type semiconductor regions 15 are formed in the p-typewell 2 of the peripheral circuit section. In addition, p⁻-typesemiconductor regions 16 are formed by the ion implantation of B (boron)into the n-type well 3 of the peripheral circuit section. In the processso far, the memory cell selecting MISFET Qt is approximately completed.

[0116] Next, as shown in FIGS. 14 and 15, a thin silicon nitride film10A with a thickness of about 10 to 15 nm is deposited on the substrate1 by the CVD method, and then, a silicon oxide film 21A with a thicknessof about 70 nm is deposited thereon by the CVD method. By so doing, thespaces of the gate electrodes 7 (word lines WL) are filled with thesilicon oxide film 21A. The silicon oxide film 21A is deposited to thethickness larger than the half of the depth of the spaces between thegate electrodes 7 (word lines WL) so as not to form any voids in thespaces. The silicon nitride film 10A is used as an etching stopper toprevent the silicon oxide film 5 in the device isolation trench 4 frombeing etched when performing the dry etching to form the contact holes(openings) in the spaces of the gate electrodes 7 in the latter step.Therefore, it is possible to omit the silicon nitride film 10A in such acase where the amount of etching of the silicon oxide film 5 does notmatter.

[0117] Next, as shown in FIG. 16, two-layered sidewall insulating films21 and 10 are formed on the sidewalls of the gate electrodes 7 by theanisotropic etching of the silicon oxide film 21A and the siliconnitride film 10A of the peripheral circuit section. Subsequently, asshown in FIG. 17, the n⁺-type semiconductor regions (source and drainregions) 17 are formed by the ion implantation of P (phosphorus) intothe p-type well 2 of the peripheral circuit section, and the p⁺-typesemiconductor regions (source and drain regions) 18 are formed by theion implantation of B (boron) into the n-type well 3. In the process sofar, the n-channel MISFET Qn and the p-channel MISFET Qp areapproximately completed.

[0118] Next, as shown in FIGS. 18 and 19, after depositing a thicksilicon oxide film 22 with a thickness of about 600 nm on the substrate1 by the CVD method, this silicon oxide film 22 is polished andplanarized by the chemical mechanical polishing method. By so doing, thesurface height of the silicon oxide film 22 is made uniform in thememory array and the peripheral circuit section. In this case, it isalso possible to recede the surface height of the silicon oxide film 22to the upper surface of the cap insulating film 9 by using the siliconnitride film which forms a part of the cap insulating film 9 as astopper of the polishing.

[0119] Next, as shown in FIGS. 20 and 21 (sectional view taken along theline B-B in FIG. 9), a thin silicon oxide film 23 with a thickness ofabout 10 nm is deposited on the silicon oxide film 22 by the CVD method,and subsequently, a polycrystalline silicon film 24A with a thickness ofabout 70 nm is deposited on the silicon oxide film 23 by the CVD method.Thereafter, an anti-reflection film 25 with a thickness of about 60 nmand a photoresist film 26 with a thickness of about 400 nm arespin-coated on the polycrystalline silicon film 24A. The silicon oxidefilm 23 is deposited to repair the small scratches on the surface of thesilicon oxide film 22 created when polishing the silicon oxide film 22by the chemical mechanical polishing method.

[0120] Next, as shown in FIGS. 22 and 23, the anti-reflection film 25and the polycrystalline silicon film 24A are partially dry-etched withusing the photoresist film 26 as a mask, thereby forming an etchingresistant mask 24. FIG. 24 is a plan view showing a pattern (portionapplied to gray color) of the etching resistant mask 24 made of thepolycrystalline silicon film 24A. As shown in FIG. 24, the etchingresistant mask 24 has elongated slit-shaped or trench-shaped openings 27crossing the memory array and extending in the longitudinal direction ofthe active region L. The reason why the slit-shaped (trench-shaped)openings 27 are provided in the etching resistant mask 24 for formingthe contact holes 12 and 13 in the spaces of the gate electrodes 7 willbe described later.

[0121] Next, as shown in FIGS. 25 and 26, after the removal of thephotoresist film 26 and the anti-reflection film 25, the silicon oxidefilms 23, 22, and 21A in the openings 27 are dry-etched with using theetching resistant mask 24 as a mask, thereby forming the contact holes(openings) 12 and 13 on the n-type semiconductor regions (source anddrain regions) 8, more specifically, in the spaces between the gateelectrodes 7. One of the contact holes 12 and 13 (contact hole 12) isused to connect one of the n-type semiconductor regions (source anddrain regions) 8 to the bit line BL, and the other of them (contact hole13) is used to connect the other of the n-type semiconductor regions(source and drain regions) 8 to the lower electrode 41 of the datastorage capacitor C.

[0122] The dry etching of the silicon oxide films 23, 22, and 21A isperformed with using the silicon nitride film which forms a part of thecap insulating film 9 and the silicon nitride film 10A as etchingstoppers. In this manner, it is possible to prevent the problem that thesilicon oxide film 5 in the device isolation trench 4 is etched whenperforming the dry etching of the silicon oxide-films 21A, 22, and 23and also possible to prevent the problem that the cap insulating film 9is etched and the upper surface of the gate electrode 7 (word line WL)is exposed. In addition, the sidewall insulating film 10 made of thesilicon nitride film 10A is formed on the sidewall of the gate electrode7 (word line WL) by this dry etching.

[0123] Next, as shown in FIGS. 27 and 28, a silicon oxide film 11A witha thickness of about 30 nm is deposited on the substrate 1 by the CVDmethod. Thereafter, the sidewall insulating film 11 made of the siliconoxide film 11A is formed on the sidewall of the gate electrode 7 (wordline WL) by the anisotropic etching of the silicon oxide film 11A asshown in FIG. 29. At this time, as shown in FIG. 30, the sidewallinsulating film 11 made of the silicon oxide film 11A is formed also onthe sidewalls of the silicon oxide films 22 and 21A along the extensiondirection of the slit-shaped (trench-shaped) openings 27.

[0124] The anisotropic etching of the silicon oxide film 11A isperformed with using the sidewall insulating film 10 made of siliconnitride and the silicon nitride film forming a part of the capinsulating film 9 as etching stoppers. By doing so, the height of thesidewall insulating film 11 formed on the sidewall of the gate electrode7 (word line WL) becomes lower than the upper surface of the capinsulating film 9 (FIG. 29). In addition, it is desirable that theetching amount in the anisotropic etching of the sidewall insulatingfilm 11 is controlled in consideration of the thickness reduction of thecap insulating film 9 due to the chemical mechanical polishing performedlater with using the silicon nitride film of the cap insulating film 9as a stopper. More specifically, it is preferable to sufficiently ensurethe difference in height between the upper surface of the sidewallinsulating film 11 and the upper surface of the cap insulating film 9 sothat the upper surface of the sidewall insulating film 11 made ofsilicon oxide surely becomes lower than the upper surface of the capinsulating film 9 even after the chemical mechanical polishing.Meanwhile, the upper end portion of the sidewall insulating film 11formed on the sidewall of the silicon oxide films 22 and 21A is higherthan that of the sidewall insulating film 11 formed on the sidewall ofthe gate electrode 7 (word line WL) (FIG. 30).

[0125] In the process so far, two-layered sidewall insulating films 10and 11 comprised of a thin silicon nitride film (10A) and a siliconoxide film (11A) with a thickness larger than that of the siliconnitride film are formed on the sidewall of the gate electrode 7 (wordline WL) of the memory cell selecting MISFET Qt. Also, since the heightof the sidewall insulating film 11 made of a silicon oxide film (11A) onthe sidewall of the gate electrode 7 (word line WL) is lower than theupper surface of the cap insulating film 9, the diameter (a) in theupper portion of the section along the direction of the gate length ofthe contact holes 12 and 13 formed in the spaces of the gate electrodes7 (word lines WL) is larger than the diameter (b) in the bottom of thesame (a>b).

[0126] Next, as shown in FIGS. 31 and 32, the thin silicon nitride film10A left at the bottom of the contact holes 12 and 13 is removed by thedry etching to expose the surface of the n-type semiconductor regions(source and drain regions) 8. Subsequently, the surface of the n-typesemiconductor regions (source and drain regions) 8 damaged by the dryetching is thinly dry-etched to remove the damage. Thereafter, thesurface is cleaned by the use of hydrofluoric acid.

[0127] Next, as shown in FIGS. 33 and 34, an n-type polycrystallinesilicon film 14A with a thickness of about 100 nm doped with P(phosphorus) is deposited by the CVD method to fill the contact holes 12and 13 with the n-type polycrystalline silicon film 14A. Note that ifcontact holes with a diameter larger than those of the contact holes 12and 13 are provided in the peripheral circuit section, there is thepossibility that the thickness of the n-type polycrystalline siliconfilm 14A in the contact holes becomes insufficient and the substrate 1at the bottom of the contact hole is removed when polishing the n-typepolycrystalline silicon film 14A in the subsequent process. Therefore,it is also preferable to deposit a silicon oxide film with a thicknessof about 200 nm further on the n-type polycrystalline silicon film 14Aby the CVD method.

[0128] Next, as shown in FIGS. 35 and 36, the n-type polycrystallinesilicon film 14A, the etching resistant mask 24 made of thepolycrystalline silicon, and the underlying silicon oxide films 21A, 22,and 23 are polished by the chemical mechanical polishing. By so doing,the n-type polycrystalline silicon film 14A outside the contact holes 12and 13 is removed, and the plugs 14 made of the n-type polycrystallinesilicon film 14A are formed in the contact holes 12 and 13. Thischemical mechanical polishing is performed with using the siliconnitride film forming a part of the cap insulating film 9 as a stopper.

[0129] As described above, in this embodiment, the silicon oxide films21A, 22, and 23 are dry-etched by the use of the etching resistant mask24 having the slit-shaped (trench-shaped) openings 27 extending in thelongitudinal direction of the active regions L. By doing so, the contactholes (openings) 12 and 13 are formed in the spaces of the gateelectrodes 7. Next, the sidewall insulating films 11 made of the siliconoxide film 11A are formed on the sidewalls of the gate electrodes 7 andon the sidewalls of the silicon oxide films 22 and 21A which constitutethe sidewall surfaces of the contact holes 12 and 13. Thereafter, theplugs 14 are formed in the contact holes 12 and 13.

[0130] In addition, since the laminated structure in which a part of thecap insulating film 9 is formed of a silicon nitride film is used inthis embodiment, it is possible to use the silicon nitride film as astopper when performing the chemical mechanical polishing to the n-typepolycrystalline silicon film 14A. Therefore, it is possible to easilycontrol the thickness of the cap insulating film 9.

[0131] Furthermore, the cap insulating film 9 in this embodiment has alaminated structure in which a silicon oxide film is provided below thesilicon nitride film used as a stopper in the chemical mechanicalpolishing. Therefore, it is possible to ensure the thickness-of the capinsulating film 9 at the end of the chemical mechanical polishing, whilereducing the thickness of the silicon nitride film that is undesirablefrom the viewpoint of the etching selectivity to the resist and that tothe tungsten when processing the gate electrode 7.

[0132]FIG. 37A is a schematic plan view of the contact hole 12 formed bythe use of the etching resistant mask 24 having the slit-shaped(trench-shaped) opening 27. Since the sidewall insulating film 11 madeof a silicon oxide film is formed on the sidewall of the contact hole12, the region inside the sidewall insulating film 11 (portion appliedto gray color) serves as the region at which the n-type semiconductorregion 8 exposed at the bottom of the contact hole 12 comes into contactwith the plug 14.

[0133] Meanwhile, FIG. 37B is a schematic plan view of the contact hole12 formed by the use of the etching resistant mask having thehole-shaped opening 30 in the contact hole opening region. Also in thiscase, the sidewall insulating film 11 is formed on the sidewall of thecontact hole 12. Therefore, the region inside the sidewall insulatingfilm 11 (portion applied to gray color) serves as the region at whichthe n-type semiconductor region 8 exposed at the bottom of the contacthole 12 comes into contact with the plug 14. However, in the case of thecontact hole 12 formed by the use of the etching resistant mask withsuch a hole-shaped opening 30, when the position of the opening 30 isshifted in the longitudinal direction of the active region L due to themisalignment of the photomask, the region at which the n-typesemiconductor region 8 comes into contact with the plug 14 becomes smallas shown in FIG. 37C. Contrary to this, in the case of the contact hole12 formed by the use of the etching resistant mask with the slit-shaped(trench-shaped) opening 27 extending in the longitudinal direction ofthe active region L, the region at which the n-type semiconductor region8 comes into contact with the plug 14 does not become small even whenthe position of the opening 27 is shifted in the longitudinal directionof the active region L due to the misalignment of the photomask. Morespecifically, according to this embodiment in which the contact hole 12is formed by the use of the etching resistant mask having theslit-shaped (trench-shaped) opening 27, it is possible to ensure theutmost contact area between the plug 14 filled into the contact hole 12and the n-type semiconductor region 8. Therefore, it is possible toprevent the increase of the contact resistance between the plug 14 andthe n-type semiconductor region 8.

[0134] The difference in contact area between the plug 14 and the n-typesemiconductor region 8 due to the shape of the opening formed in theetching resistant mask differs between the case where the sidewallinsulating film is formed on the sidewall of the gate electrode and thenforming the contact hole in the spaces of the gate electrodes like thatin the conventional self align contact (SAC) technique and the casewhere the contact hole is formed in the spaces of the gate electrodesand then forming the sidewall insulating film on the sidewall of thegate electrode like that in this embodiment.

[0135] Next, as shown in FIGS. 38 and 39, a silicon nitride film 19 witha thickness of about 20 nm is deposited over the substrate 1 by the CVDmethod, and then, a silicon oxide film 31 with a thickness of about 300nm is deposited on the silicon nitride film 19 by the CVD method.Thereafter, about 100 nm of the silicon oxide film 31 is polished by thechemical mechanical polishing method so as to planarize the surfacethereof. The planarization of the silicon oxide film 31 is performedwith an aim to increase the accuracy of the formation of the throughholes (32 and 36) formed over the memory cell selecting MISFET Qt in thelatter process.

[0136] Next, as shown in FIGS. 40 and 41, the silicon oxide film 31 onthe contact holes 12 is dry-etched with using the photoresist film 28 asa mask. The dry etching of the silicon oxide film 31 is performed withusing the underlying silicon nitride film 19 as an etching stopper. Morespecifically, this dry etching is performed under the condition that theetching selectivity of the silicon oxide film 31 with respect to thesilicon nitride film 19 is high so as not to completely remove thesilicon nitride film 19 above the contact holes 12.

[0137] Next, as shown in FIGS. 42, 43, and 44, the silicon nitride film19 above the contact holes 12 is dry-etched with using the photoresistfilm 28 as a mask, thereby forming through holes 32 above the contactholes 12. The dry etching of the silicon nitride film 19 is performedunder the condition that the etching selectivity with respect to thesilicon oxide film is high.

[0138] The reason why the silicon nitride film 19 is provided below thesilicon oxide film 31 will be described here with reference to FIG. 45and 46. FIG. 45 is a sectional view taken along the line A-A (in thelongitudinal direction of the active region L) in FIG. 42, and FIG. 46is a sectional view taken along the line B-B (in the extension directionof the word line WL) in FIG. 42. Both of them show the case where thesilicon nitride film 19 is not provided below the silicon oxide film 31.

[0139] In the section (FIG. 45) along the longitudinal direction of theactive region L, the upper portions of the gate electrodes 7 (word linesWL) are covered with the cap insulating films 9 including the siliconnitride film. Therefore, even in the case where the position of thethrough hole 32 and that of the underlying contact hole 12 are shiftedwhen performing the dry etching of the silicon oxide film 31 on thecontact holes 12 with using the photoresist film 28 as a mask, the capinsulating film 9 serves as the etching stopper, and hence, the bottomsurface of the through hole 32 is little receded below the upper surfaceof the cap insulating film 9.

[0140] Meanwhile, in the section (FIG. 46) along the extension directionof the word line WL, the silicon nitride film (19) serving as an etchingstopper is not provided below the contact holes 12. Therefore, when thesilicon oxide film 31 is etched, the underlying silicon oxide film 22and the sidewall insulating film 11 made of silicon oxide are alsoetched, and thus, the bottom surface of the through hole 32 is largelyreceded below the upper surface of the cap insulating film 9 (positionspointed out by the arrows in FIG. 46). As a result, the distance betweenthe plug 33 and the gate electrode 7 (word line WL) is shortened whenfilling the plug 33 made of metal into the through hole 32 and formingthe bit line BL on the plug in the later-described process.Consequently, the capacitance formed between the bit line BL and thegate electrode 7 (word line WL) is increased.

[0141] Contrary to this, in the case where the silicon nitride film 19is provided below the silicon oxide film 31 like in this embodiment, thesilicon oxide film 22 at the bottom of the through holes 32 and thesidewall insulating films 11 are etched only a little as shown in FIG.44. Consequently, it is possible to sufficiently ensure the distancebetween the plug 33 filled into the through hole 32 and the gateelectrode 7 (word line WL) and also possible to prevent the increase ofthe capacitance formed between the bit line BL and the gate electrode 7(word line WL).

[0142] Next, as shown in FIG. 47, the silicon oxide film 31, the siliconnitride film 19, and the silicon oxide film 22 in the peripheral circuitsection are sequentially etched with using the photoresist film 29formed on the silicon oxide film 31 as a mask, thereby forming contactholes 48 on the n⁺-type semiconductor regions (source and drain regions)17 of the n-channel MISFET Qn and forming contact holes 49 on thep⁺-type semiconductor regions (source and drain regions) 18 of thep-channel MISFET Qp.

[0143] Next, as shown in FIGS. 48 to 50, the plugs 33 are formed in thethrough holes 32 and-the contact holes 48 and 49. The plug 33 is formedin the following manner. For example, a barrier metal film made of TiNis deposited on the silicon oxide film 31 by the CVD method, and then, aW film is deposited on the barrier metal film by the CVD method to fillthese films into the through holes 32 and the contact holes 48 and 49.Thereafter, these films outside the through holes 32 and the contactholes 48 and 49 are removed by the chemical mechanical polishing method.

[0144] Next, as shown in FIGS. 51 to 53, bit lines BL are formed on thesilicon oxide film 31. Also, as shown in FIG. 54, first layer wirings 44to 47 are formed on the silicon oxide film 31 in the peripheral circuitsection. The bit lines BL and the first layer wirings 44 to 47 areformed in the following manner. That is, a TiN film (or WN film) with athickness of about 10 nm and a W film with a thickness of about 50 nmare deposited on the silicon oxide film 31 by the sputtering method.Thereafter, these films are dry-etched with using a photoresist film asa mask. The bit line BL is electrically connected to one of the n-typesemiconductor regions (source and drain regions) 8 of the memory cellselecting MISFET Qt via the plug 33 filled into the through hole 32 andthe plug 14 filled into the contact hole 12.

[0145] As described above, in the DRAM according to this embodiment, thesidewall insulating film 10 made of a silicon nitride film and thesidewall insulating film 11 made of a silicon oxide film are formed onthe sidewall of the gate electrode 7 of the memory cell selecting MISFETQt, and the plugs 14 are filled into the spaces (contact holes 12 and13) of the gate electrodes 7 surrounded by these sidewall insulatingfilms 10 and 11. By doing so, it is possible to reduce the effectiverelative dielectric constant of the sidewall insulating film incomparison with the conventional self align contact (SAC) technique inwhich the sidewall insulating film is formed of only the silicon nitridefilm having the relative dielectric constant higher than that of thesilicon oxide film. Therefore, it is possible to reduce the capacitanceto the word line serving as the major component of the bit linecapacitance.

[0146] Also, in the DRAM according to this embodiment, the capinsulating film 9 on the gate electrode 7 is formed of a laminated filmof a silicon oxide film and a silicon nitride film. By doing so, it ispossible to reduce the effective relative dielectric constant of the capinsulating film in comparison with the conventional self align contact(SAC) technique in which the cap insulating film is formed of only thesilicon nitride film having the relative dielectric constant higher thanthat of the silicon oxide film. Therefore, it is possible to furtherreduce the capacitance to the word line in the bit line capacitance.

[0147] Also, in the DRAM according to this embodiment, when forming thethrough holes 32 by the etching of the silicon oxide film 31 below thebit lines BL, the silicon nitride film 19 to be an etching stopper isformed below the silicon oxide film 31 in advance so as to reduce theremoval of the silicon oxide film 22 at the bottom of the through holes32 and the sidewall insulating film 11. In this manner, since it ispossible to ensure the distance between the plugs 33 filled into thethrough holes 32 and the gate electrodes 7 (word lines WL), it ispossible to further reduce the capacitance to the word line in the bitline capacitance.

[0148] Next, as shown in FIG. 55, the silicon oxide film 34 with athickness of about 300 nm is deposited on the bit lines BL by the CVDmethod, and then, the surface of the silicon oxide film 34 is planarizedby the chemical mechanical polishing method. Subsequently, the siliconnitride film 35 with a thickness of about 50 nm is deposited on thesilicon oxide film 34 by the CVD method, and then, the silicon nitridefilm 35, the silicon oxide films 34 and 31, and the silicon nitride film19 are sequentially dry-etched, thereby forming through holes 36 on thecontact holes 13 into which the plugs 14 are filled.

[0149] Also in this case, since the silicon nitride film 19 is formedbelow the silicon oxide film 31 and the silicon nitride film 19 servesas the etching stopper, it is possible to reduce the removal of thesilicon oxide film 22 at the bottom of the through holes 36 even in thecase where the positions of the through holes 36 and those of thecontact holes 13 are shifted due to the misalignment of the photomask.In this manner, it is possible to ensure the distance between the plugs37 to be filled into the through holes 36 in the following process andthe gate electrodes 7 (word lines WL). Therefore, it is possible toprevent the increase of the capacitance formed between the data storagecapacitor C formed on the through holes 36 in the latter process and thegate electrodes 7 (word lines WL) and also possible to reduce the delayof the gate electrodes 7 (word lines WL).

[0150] Next, the plugs 37 are formed in the through holes 36, and then,the barrier metal films 38 are formed on the surfaces of the plugs 37.The plug 37 and the barrier metal film 38 are formed in the followingmanner. That is, an n-type polycrystalline silicon film doped with P isdeposited on the silicon nitride film 35 by the CVD method to fill then-type polycrystalline silicon film into the through holes 36.Thereafter, the n-type polycrystalline silicon film outside the throughholes 36 is removed by the dry etching. At this time, the n-typepolycrystalline silicon film in the through hole 36 is over-etched torecede the surface of the plug 37 below the surface of the siliconnitride film 35, thereby ensuring the spaces on the plugs 37 into whichthe barrier metal films 38 are filled. Next, a TiN film is deposited onthe silicon nitride film 35 by the sputtering method, thereby filling aTaN (tantalum nitride) film on the plugs 37 into the through holes 36.Thereafter, the TaN film outside the through holes 36 is removed by thechemical mechanical polishing method.

[0151] The barrier metal film 38 interposed between the lower electrodeof the data storage capacitor C formed above the through hole 36 in thelatter process and the plug 37 is formed with an aim to reduce theundesired reaction at the interface between the Ru film forming thelower electrode and the polycrystalline silicon film forming the plug 37at the time of the high-temperature treatment performed in the processof forming the capacitor insulating film of the data storage capacitorC.

[0152] As described above, the outer sidewall insulating film 11 of thetwo-layered sidewall insulating films 10 and 11 formed on the sidewallof the gate electrode 7 has the height lower than that of the uppersurface of the cap insulating film 9. Therefore, the diameter of theupper portion of the contact holes 12 and 13 in the section along thedirection of the gate length is larger than the diameter of the bottomof the same (see FIG. 29). More specifically, the diameter of the plug14 filled into the contact holes 12 and 13 is larger in the upperportion in comparison with that in the bottom portion of the contactholes 12 and 13.

[0153] In this manner, even in the case where the center of the throughhole 36 is shifted from the center of the contact hole 13 due to themisalignment of the photomask when forming the through hole 36 above thecontact hole 13, since the surface area of the contact hole 13 is large,it is possible to sufficiently ensure the contact area therebetween.

[0154] Next, as shown in FIG. 56, the data storage capacitor C comprisedof the lower electrode 41, the capacitor insulating film 42, and theupper electrode 43 is formed above the through hole 36, and the lowerelectrode 41 of the data storage capacitor C is electrically connectedto the other of the n-type semiconductor regions (source and drainregions) 8 of the memory cell selecting MISFET Qt via the plug 37 filledinto the through hole 36 and the plug 14 filled into the contact hole13. Then, the memory cell is approximately completed.

[0155] The data storage capacitor C is formed in the following manner.First, a thick silicon oxide film 39 with a thickness of about 1 μm isdeposited on the silicon nitride film 35 by the CVD method, andsubsequently, the silicon oxide film 39 is dry-etched with using aphotoresist film (not shown) as a mask, thereby forming the trench 40 onthe through holes 36. The etching of the silicon oxide film 39 isperformed with using the silicon nitride film 35 as an etching stopperso as not to etch the underlying silicon oxide film 34.

[0156] Next, an Ru film with a thickness about 70 to 80 nm is depositedon the silicon oxide film 39 and in the trench 40 by the CVD method.Then, after filling a photoresist film into the trench 40 with an aim toprevent the removal of the Ru film in the trench 40, the Ru film outsidethe trench 40 not covered with the photoresist film is removed by thedry etching, and the photoresist film filled into the trench 40 isremoved by the ashing. By doing so, the lower electrode 41 made of theRu film is formed on the sidewall and the bottom surface of the trench40.

[0157] Next, a capacitor insulating film 42 is formed on the siliconoxide film 39 and in the trench 40 in which the lower electrode isformed on the sidewall thereof. The capacitor insulating film 42 is madeof, for example, a BST film with a thickness of about 20 nm deposited bythe CVD method. In addition to the BST film, the ferroelectric (highdielectric) film made of perovskite metal oxide such as BaTiO₃ (bariumtitanate), PbTiO₃ (lead titanate), PZT, PLT, and PLZT is also availableto form the capacitor insulating film 42.

[0158] Next, the upper electrode 43 is formed over the capacitorinsulating film 42. The upper electrode 43 is made of, for example, anRu film with a thickness of about 200 nm deposited by the CVD method orthe sputtering method. In the process so far, the data storage capacitorC comprised of the lower electrode 41 made of an Ru film, the capacitorinsulating film 42 made of a BST film, and the upper electrode 43 madeof an Ru film is completed.

[0159] Next, as shown in FIG. 57, a silicon oxide film 51 is depositedon the data storage capacitor C by the CVD method. Thereafter, as shownin FIG. 58, the silicon oxide films 51 and 39, the silicon nitride film35, and the silicon oxide film 34 in the peripheral circuit section aresequentially etched to form the through hole 55 on the first layerwiring 44, and then, the plug 56 is formed in the through hole 55. Theplug 56 is comprised of the laminated film of, for example, a TiN filmand a W film.

[0160] Thereafter, an Al alloy film formed on the silicon oxide film 51by the sputtering method is patterned to form Al alloy wirings 52 to 54,thereby approximately completing the DRAM shown in FIGS. 2 and 3.

Second Embodiment

[0161] The manufacturing method of DRAM according to the secondembodiment will be described with reference to FIGS. 59 to 62 along themanufacturing process. First, as shown in FIG. 59, the memory cellselecting MISFET Qt is formed in the memory array and the n-channelMISFET Qn and the p-channel MISFET Qp are formed in the peripheralcircuit section in the same manner as that of the first embodiment.Thereafter, the silicon oxide films 22 and 23 are formed thereon, andthe etching resistant mask 24 made of a polycrystalline silicon film isformed on the silicon oxide film 23. The process so far is the same asthat of the first embodiment shown in FIGS. 4 to 24.

[0162] Next, as shown in FIG. 60, the silicon oxide films 21A, 22, and23 are dry-etched with using the etching resistant mask 24 as a mask,thereby forming the contact holes (openings) 12 and 13 in the spaces ofthe gate electrodes 7. At this time, the silicon nitride film 10Acovering the n-type semiconductor regions (source and drain regions) 8is also etched to expose the surfaces of the n-type semiconductorregions (source and drain regions) 8 at the bottom of the contact holes(openings) 12 and 13. Similar to the first embodiment, in the process sofar, the sidewall insulating film 10 made of the silicon nitride film10A is formed on the sidewall of the gate electrode 7 (word line WL).

[0163] Next, the surface of the n-type semiconductor regions (source anddrain regions) 8 damaged by the dry etching is thinly dry-etched andthen cleaned by the hydrofluoric acid. Thereafter, as shown in FIG. 61,the silicon oxide film 11A with a thickness of about 30 nm is depositedon the substrate 1 by the CVD method, and subsequently, as shown in FIG.62, the sidewall insulating film 11 made of the silicon oxide film 11Awith a thickness of about 30 nm is formed on the sidewall of the gateelectrode 7 (word line WL) by performing the anisotropic etching of thesilicon oxide film 11A. The following process is the same as that of thefirst embodiment.

[0164] As described above, in the manufacturing method according to thisembodiment, the sidewall insulating film 11 is formed on the sidewall ofthe gate electrode 7 (word line WL) after removing the silicon nitridefilm 10A at the bottom of the contact holes 12 and 13. Therefore, thesilicon nitride film 10A is not left at the bottom of the sidewallinsulating film 11 (FIG. 62).

[0165] Meanwhile, in the manufacturing method according to the firstembodiment in which the silicon nitride film 10A at the bottom of thecontact holes 12 and 13 is removed after forming the sidewall insulatingfilm 11 on the sidewall of the gate electrode 7 (word line WL), thesilicon nitride film 10A is left at the bottom of the sidewallinsulating film 11 (FIG. 31). When the silicon nitride film 10A is lefton the edge portion of the sidewall of the gate electrode 7 (word lineWL) like this, the interface between the silicon nitride film 10A andthe underlying gate insulating film 6 becomes charged, which causes thevariation of the leakage current of the memory cell.

[0166] Therefore, in the manufacturing method according to thisembodiment in which the silicon nitride film 10A is not left on the edgeportion of the sidewall of the gate electrode 7 (word line WL), it ispossible to prevent such a problem and also to reduce the characteristicvariation of the memory cell.

Third Embodiment

[0167] The manufacturing method of-DRAM according to the thirdembodiment will be described with reference to FIGS. 63 to 80 along themanufacturing process. First, as shown in FIGS. 63 and 64, the memorycell selecting MISFET Qt is formed in the memory array and the n-channelMISFET Qn and the p-channel MISFET Qp are formed in the peripheralcircuit section in the same manner as that in the first embodiment.Thereafter, the silicon oxide film 22 deposited thereon is polished andplanarized by the chemical mechanical polishing method. The process sofar is identical to that in the first embodiment shown in FIGS. 4 to 19.However, in this embodiment, the silicon nitride film forming a part ofthe cap insulating film 9 is used as a stopper of the polishing, and theheight of the surface of the silicon oxide film 22 is receded to theupper surface of the cap insulating film 9.

[0168] Next, as shown in FIGS. 65 to 67, the silicon oxide film 23 isdeposited on the silicon oxide film 22 by the CVD method. Thereafter,the silicon oxide films 23, 22, and 21A are dry-etched with using thephotoresist film 60 formed on the silicon oxide film 23 as a mask,thereby forming round contact holes (openings) 61 and 62 on the n-typesemiconductor regions (source and drain regions) 8, that is, in thespaces of the gate electrodes 7. The dry etching of the silicon oxidefilms 23, 22, and 21A is performed with using the silicon nitride filmforming a part of the cap insulating film 9 and the silicon nitride film10A as etching stoppers. In this manner, it is possible to prevent theproblem that the silicon oxide film 5 in the device isolation trench 4is removed when performing the dry etching of the silicon oxide films21A, 22, and 23 and also possible to prevent the problem that the capinsulating film 9 is removed and the upper surface of the gate electrode7 (word line WL) is exposed. In addition, by the above-described dryetching, the sidewall insulating film 10 made of the silicon nitridefilm 10A is formed on the sidewall of the gate electrode 7 (word lineWL).

[0169] As described above, in this embodiment, the round contact holes(openings) 61 and 62 are formed in the spaces of the gate electrodes 7by the dry etching performed with using the photoresist film 60 formedon the silicon oxide film 23 as a mask. Consequently, it is possible toreduce the number of process in comparison with the first embodiment inwhich the contact holes (openings) 12 and 13 are formed in the spaces ofthe gate electrodes 7 by the dry etching performed with using theetching resistant mask 24 made of a polycrystalline silicon film as amask.

[0170] Next, as shown in FIGS. 68 and 69, the sidewall insulating film11 is formed on the sidewall of the gate electrode 7 (word line WL) bythe anisotropic etching of the silicon oxide film deposited on thesubstrate 1. As described above, in this embodiment, the height of thesurface of the silicon oxide film 22 is receded to the upper surface ofthe cap insulating film 9 (see FIG. 63) when polishing and planarizingthe silicon oxide film 22. Therefore, the height of the sidewallinsulating film 11 becomes uniform in both the longitudinal direction ofthe active region (A-A direction) and the extension direction of thegate electrode 7 (word line WL) (B-B direction) crossing to each other.Also, the upper end of the sidewall insulating film 11 is set at theposition lower than that of the upper surface of the cap insulating film9.

[0171] Next, as shown in FIGS. 70 and 71, the thin silicon nitride film10A left at the bottom of the contact holes 61 and 62 is removed by thedry etching to expose the surfaces of the n-type semiconductor regions(source and drain regions) 8. Thereafter, the n-type polycrystallinesilicon film doped with, for example, P (phosphorus) is filled into thecontact holes 61 and 62, thereby forming the plugs 14.

[0172] In the manufacturing method according to this embodiment, theupper end of the sidewall insulating film 11 is lower than the uppersurface of the cap insulating film 9 in every direction. Therefore, thesurfaces of the plugs 14 filled into the contact holes 61 and 62 have asurface area larger than that of the first embodiment. Morespecifically, both the contact area between the contact hole 61 and thethrough hole 32 formed thereon and that between the contact hole 62 andthe through hole 36 formed thereon are larger than those in the firstembodiment.

[0173] Next, as shown in FIGS. 72 and 73, the silicon nitride film 19with a thickness of about 20 nm is deposited on the substrate 1 by theCVD method, and subsequently, the silicon oxide film 31 with a thicknessof about 300 nm is deposited on the silicon nitride film 19 by the CVDmethod. Thereafter, about 100 nm of the silicon oxide film 31 ispolished by the chemical mechanical polishing method to planarize thesurface thereof.

[0174] Next, as shown in FIGS. 74 and 75, the silicon oxide film 31 onthe contact hole 61 is dry-etched with using the photoresist film 28 asa mask. The dry etching of the silicon oxide film 31 is performed withusing the underlying silicon nitride film 19 as an etching stopper. Morespecifically, this dry etching is performed under the condition that theetching selectivity of the silicon oxide film 31 with respect to thesilicon nitride film 19 is high, and the silicon nitride film 19 on thecontact holes 61 is not completely removed.

[0175] Next, as shown in FIGS. 76, 77, and 78, the through holes 32 areformed on the contact holes 61 by the dry etching of the silicon nitridefilm 19 on the contact holes 61 with using the photoresist film 28 as amask. The dry etching of the silicon nitride film 19 is performed underthe condition that the etching selectivity with respect to the siliconoxide film is high.

[0176] As described above, due to the silicon nitride film 19 providedbelow the silicon oxide film 31, the silicon oxide film 22 at the bottomof the through hole 32 and the sidewall insulating film 11 are removedonly slightly. Therefore, similar to the first embodiment, it ispossible to ensure the distance between the plug 33 filled into thethrough hole 32 and the gate electrode 7 (word line WL) and alsopossible to prevent the increase of the capacitance formed between thebit line BL and the gate electrode 7 (word line WL).

[0177] Next, as shown in FIGS. 79 and 80, the plugs 33 are formed in thethrough holes 32 in the manner as described above. Since the followingprocess is the same as that in the first embodiment, the descriptionthereof will be omitted.

[0178] In the foregoing, the invention made by the inventor of thepresent invention has been concretely described based on theembodiments. However, it is needless to say that the present inventionis not limited to the foregoing embodiments and various modificationsand alterations can be made within the scope of the present invention.

[0179] In the foregoing embodiments, the case where the presentinvention is applied to DRAM has been described. However, the presentinvention is not limited to this. More specifically, the presentinvention can be applied to the manufacturing method of a semiconductorintegrated circuit device including the process of performing theetching of the silicon oxide film, which covers the gate electrodes, toform the contact holes (openings) in the space of the gate electrodes,in the case where at least a part of the sidewall insulating film of thegate electrode is formed of a silicon oxide film.

INDUSTRIAL APPLICABILITY

[0180] According to the present invention, since the bit linecapacitance can be reduced, it is possible to increase the signalvoltage when reading the charge (data) stored in the data storagecapacitor. Therefore, the noise margin of the signal is increased andthe refresh cycle is extended. Also, it is possible to reduce the powerconsumption.

[0181] In addition, since the number of memory cells connected to onebit line can be increased, the number of sense amplifiers can bereduced. Therefore, it is possible to reduce the chip area, and thus, itis possible to increase the number of chips obtained per one wafer andalso to improve the manufacturing yield.

What is claimed is:
 1. A method of manufacturing a semiconductorintegrated circuit device comprising the steps of: (a) forming a firstconductor layer over a semiconductor substrate and then processing saidfirst conductor layer into a predetermined shape, thereby forming firstconductor pieces in a first region of said semiconductor substrate; (b)forming a first insulating film over said first conductor pieces and thesaid semiconductor substrate; (c) forming first openings in said firstinsulating film so as to be located at positions between said firstconductor pieces; (d) forming first sidewall insulating films made of asilicon oxide film on respective sidewalls of said first openings; (e)filling a second conductor layer into said first openings in which saidfirst sidewall insulating films are formed, thereby forming secondconductor pieces in said first openings; (f) forming a second insulatingfilm made of a silicon nitride film over said first and second conductorpieces; (g) forming a third insulating film made of a silicon oxide filmover said second insulating film; (h) forming second openings in saidthird insulating film and said second insulating film above said firstopenings, thereby exposing said second conductor pieces at the bottom ofsaid second openings; and (i) filling a third conductor layer into saidsecond openings, thereby forming in said second openings third conductorpieces electrically connected to said second conductor pieces.
 2. Themethod of manufacturing a semiconductor integrated circuit deviceaccording to claim 1, wherein, between said steps (a) and (b), themethod further comprises the step of: (j) forming a fourth insulatingfilm made of a silicon nitride film over said first conductor pieces andsaid semiconductor substrate, and wherein said first openings formed insaid step (c) are formed by the use of dry etching performed under thecondition that the etching selectivity of said first insulating filmwith respect to said fourth insulating film is set high.
 3. The methodof manufacturing a semiconductor integrated circuit device according toclaim 2, wherein said step (d) includes the steps of: (d-1) forming saidsilicon oxide film over said first insulating film and in said openings;and (d-2) performing anisotropic etching of said silicon oxide film,thereby forming said first sidewall insulating films made of saidsilicon oxide film on the respective sidewalls of said first openings.4. The method of manufacturing a semiconductor integrated circuit deviceaccording to claim 3, wherein, between said steps (d) and (e), themethod further comprises the step of: (k) removing some parts of saidfourth insulating film not covered with said first sidewall insulatingfilm, thereby exposing some parts of said semiconductor substrate. 5.The method of manufacturing a semiconductor integrated circuit deviceaccording to claim 1, wherein said step (a) includes the steps of: (a-1)after forming said first conductor layer over said semiconductorsubstrate, forming a fifth insulating film made of a silicon nitridefilm over said first conductor layer; and (a-2) processing said fifthinsulating film and said first conductor layer into a predeterminedshape, thereby forming said first conductor pieces covered with saidfifth insulating film in the first region of said semiconductorsubstrate.
 6. The method of manufacturing a semiconductor integratedcircuit device according to claim 1, wherein, after said step (i), themethod further comprises the step of: (l) forming a fourth conductorlayer electrically connected to said third conductor pieces over saidthird insulating film.
 7. The method of manufacturing a semiconductorintegrated circuit device according to claim 6, wherein, after said step(l), the method further comprises the step of: (m) forming a dielectricfilm over said fourth conductor layer and forming a fifth conductorlayer over said dielectric film, thereby forming a capacitor comprisedof said fourth conductor layer, said dielectric film, and said fifthconductor layer.
 8. The method of manufacturing a semiconductorintegrated circuit device according to claim 1, wherein said step (a)includes the step of: (a-3) after forming said first conductor layerover said semiconductor substrate, processing said first conductor layerinto a predetermined shape, thereby forming third conductor pieces in asecond region of said semiconductor substrate.
 9. The method ofmanufacturing a semiconductor integrated circuit device according toclaim 8, wherein said first insulating film includes a sixth insulatingfilm and a seventh insulating film formed thereon, and said step (b)includes the steps of: (b-1) forming said sixth insulating film oversaid first conductor pieces, said third conductor pieces, and saidsemiconductor substrate; (b-2) performing anisotropic etching of saidsixth insulating film, thereby forming said second sidewall insulatingfilms made of said sixth insulating film on respective sidewalls of saidthird conductor pieces; and (b-3) after forming said seventh insulatingfilm over said sixth insulating film, planarizing the upper surface ofsaid seventh insulating film.
 10. The method of manufacturing asemiconductor integrated circuit device according to claim 9, whereinthe thickness of said sixth insulating film is larger than the half ofthe space between said first conductor pieces.
 11. A method ofmanufacturing a semiconductor integrated circuit device, comprising thesteps of: (a) forming a plurality of first conductor layers extendingparallel to each other over a semiconductor substrate; (b) forming afirst insulating film made of a silicon oxide film over said pluralityof first conductor layers and said semiconductor substrate; (c) forminga plurality of first openings in said first insulating film so as to belocated at positions between said plurality of first conductor layers;(d) forming first sidewall insulating films on respective sidewalls ofsaid plurality of first openings; (e) filling a second conductor layerinto said plurality of first openings in which said first sidewallinsulating films are formed; (f) forming a second insulating film madeof a silicon nitride film over said plurality of first and secondconductor layers; (g) forming a third insulating film made of a siliconoxide film above said second insulating film; (h) forming a plurality ofsecond openings in said third insulating film and said second insulatingfilm so as to be located above each of said plurality of first openings,thereby exposing said second conductor layer at the bottom of saidplurality of second openings; and (i) forming a third conductor layer insaid plurality of second openings.
 12. The method of manufacturing asemiconductor integrated circuit device according to claim 11, wherein,between said steps (a) and (b), the method further comprises the stepof: (j) forming a fourth insulating film made of a silicon nitride filmover said plurality of first conductor layers and said semiconductorsubstrate, and wherein said first openings formed in said step (c) areformed by the use of dry etching performed under the condition that theetching selectivity of said first insulating film with respect to saidfourth insulating film is set high.
 13. The method of manufacturing asemiconductor integrated circuit device according to claim 12, whereinsaid first sidewall insulating film is made of a silicon oxide film, andsaid step (d) includes the steps of: (d-1) forming said silicon oxidefilm over said first insulating film and in said openings; (d-2)performing anisotropic etching of said silicon oxide film, therebyforming said first sidewall insulating film made of said silicon oxidefilm on the respective sidewalls of said first openings; and (d-3)removing some parts of said fourth insulating film not covered with saidfirst sidewall insulating film, thereby exposing some parts of saidsemiconductor substrate.
 14. The method of manufacturing a semiconductorintegrated circuit device according to claim 11, wherein said step (a)includes the steps of: (a-1) after forming the first conductor film oversaid semiconductor substrate, forming a fifth insulating film made of asilicon nitride film over said first conductor layer; and (a-2)processing said fifth insulating film and said first conductor film intoa predetermined shape, thereby forming said plurality of first conductorlayers covered with said fifth insulating films over said semiconductorsubstrate.
 15. The method of manufacturing a semiconductor integratedcircuit device according to claim 11, wherein, after said step (i), themethod further comprises the steps of: (k) forming a fourth conductorlayer electrically connected to said second conductor layer over saidthird insulating film; and (l) forming a dielectric film over saidfourth conductor layer and forming a fifth conductor layer over saiddielectric film, thereby forming a capacitor comprised of said fourthconductor layer, said dielectric film, and said fifth conductor layer.16. A method of manufacturing a semiconductor integrated circuit device,comprising the steps of: (a) forming a first conductive film over asemiconductor substrate and then forming a first insulating film made ofa silicon nitride film or a laminated film of a silicon oxide film and asilicon nitride film over said first conductive film; (b) performing theetching of said first conductive film and said first insulating film,thereby forming first gate electrodes in a first region of saidsemiconductor substrate and forming second gate electrodes in a secondregion of said semiconductor substrate; (c) forming a first MISFEThaving said first gate electrode in the first region of saidsemiconductor substrate; (d) forming a second insulating film made of asilicon nitride film over said first and second gate electrodes and saidsemiconductor substrate, and forming a third insulating film made of asilicon oxide film over said second insulating film; (e) forming a firstsidewall insulating film comprised of said second and third insulatingfilms on the sidewall of said second gate electrode, and then, forming asecond MISFET having said second gate electrode in the second region ofsaid semiconductor substrate; (f) forming a fourth insulating film madeof a silicon oxide film over said third insulating film, and then,planarizing the upper surface of said fourth insulating film; (g)performing the etching of said fourth, third, and second insulatingfilms in the first region of said semiconductor substrate, therebyforming first openings above the source and drain of said first MISFET;(h) forming second sidewall insulating films made of a silicon oxidefilm on the sidewalls of said first openings, and then, filling a secondconductor layer into said first openings; (i) forming a fifth insulatingfilm made of a silicon nitride film over said first and second MISFETs,and forming a sixth insulating film made of a silicon oxide film oversaid fifth insulating film; (j) forming second openings in said sixthand fifth insulating films so as to be located at the positions aboveone of the source and drain of said first MISFET, thereby exposing saidsecond conductor layer at the bottom of said second openings; and (k)filling a third conductor layer into said second openings, therebyforming third conductor layers electrically connected to said secondconductor layers in said second openings.
 17. The method ofmanufacturing a semiconductor integrated circuit device according toclaim 16, wherein third openings are formed above the source and drainof said second MISFET when forming said second openings in said step(j), and a fourth conductor layer is filled into said third openingswhen filling the third conductor layer into said second openings in saidstep (k).
 18. The method of manufacturing a semiconductor integratedcircuit device according to claim 17, wherein, after said step (k), themethod further comprises the step of: (l) over said sixth insulatingfilm, forming a first wiring electrically connected to said thirdconductor layers in said second openings and forming a second wiringelectrically connected to said fourth conductor layers in said thirdopenings.
 19. The method of manufacturing a semiconductor integratedcircuit device according to claim 18, wherein, after said step (l), themethod further comprises the steps of: (m) forming a seventh insulatingfilm over said sixth insulating film and then forming fourth openings insaid seventh, sixth, and fifth insulating films so as to be located atpositions above the other of the source and drain of said first MISFET,thereby exposing said second conductor layer at the bottom of saidfourth openings; (n) filling a fifth conductor layer into said fourthopenings; (o) forming an eighth insulating film over said seventhinsulating film and then forming fifth openings in said eighthinsulating film above said fourth openings, thereby exposing said fourthconductor layer at the bottom of said fifth openings; and (p) formingfirst electrodes electrically connected to said fourth conductor layerin said fifth openings and sequentially forming a dielectric film andsecond electrodes on said first electrodes, thereby forming a capacitorcomprised of said first electrode, said dielectric film, and said secondelectrode.
 20. The method of manufacturing a semiconductor integratedcircuit device according to claim 16, wherein said first openings areformed so as to extend above said first MISFET.
 21. The method ofmanufacturing a semiconductor integrated circuit device according toclaim 16, wherein the thickness of said second insulating film made ofsaid silicon nitride film is smaller than that of said second sidewallinsulating film made of said silicon oxide film.
 22. A semiconductorintegrated circuit device, comprising: a plurality of first conductorpieces formed to extend parallel to each other over a semiconductorsubstrate; first sidewall insulating films made of the silicon oxidefilms formed on the respective sidewalls of said plurality of firstconductor pieces; second conductor pieces formed each between saidplurality of first conductor pieces on which said first sidewallinsulating films are formed; a first insulating film made of a siliconnitride film formed over said plurality of first and second conductorpieces; a second insulating film made of a silicon oxide film formedover said first insulating film; first openings formed in said first andsecond insulating films above said plurality of second conductor pieces;and third conductor pieces formed in said plurality of first openingsand electrically connected to said second conductor pieces.
 23. Thesemiconductor integrated circuit device according to claim 22, wherein asilicon nitride film with a thickness smaller than that of said firstsidewall insulating film is interposed between the respective sidewallsof said plurality of first conductor pieces and said first sidewallinsulating film.
 24. The semiconductor integrated circuit deviceaccording to claim 22, wherein the respective upper surfaces of saidplurality of first conductor pieces are covered with third insulatingfilms made of a silicon nitride film or a laminated film of a siliconoxide film and a silicon nitride film.
 25. The semiconductor integratedcircuit device according to claim 22, wherein a capacitor is formed oversaid second insulating film, said capacitor being comprised of a firstelectrode made of a fourth conductor layer electrically connected tosaid third conductor piece; a dielectric film formed on said fourthconductor layer; and a second electrode made of a fifth conductor layerformed on said dielectric film.
 26. The semiconductor integrated circuitdevice according to claim 24, wherein the upper end of said firstsidewall insulating film is higher than the upper surface of said firstconductor piece and lower than the upper surface of said thirdinsulating film.
 27. A semiconductor integrated circuit device,comprising: a plurality of first conductor layers formed to extendparallel to each other over a semiconductor substrate; second conductorlayers arranged at predetermined intervals each between said pluralityof first conductor layers; a first insulating film made of a siliconoxide film formed each between said plurality of second conductorlayers; sidewall insulating films formed each between said firstconductor layer and said second conductor layer and between said firstconductor layer and said first insulating film; a second insulating filmmade of a silicon nitride film formed over said second conductor layerand said first insulating film; a third insulating film made of asilicon oxide film formed over said second insulating film; and thirdconductor layers formed in the openings formed in said third insulatingfilm and said second insulating film and contacted to said secondconductor layers.
 28. The semiconductor integrated circuit deviceaccording to claim 27, wherein said sidewall insulating film is made ofa silicon oxide film.
 29. The semiconductor integrated circuit deviceaccording to claim 28, wherein a second sidewall insulating film made ofa silicon nitride film is formed between the sidewall of said firstconductor layer and said sidewall insulating film.